This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.
提出了一种改进时序重排算法 ,使时序重排可以更有效地与其他组合优化算法结合起来 ,共同提高同步时序电路的速度 。
This paper proposes a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.
时序重排是一种同步时序电路性能优化的重要方法 。